--
-- Bedrock FSM - Moore version
--
library IEEE;
use IEEE.std_logic_1164.all;
entity BEDROCK is
port( CLK, RESET_N, BARNEY, WILMA, MICE : in std_logic;
FRED, DINO : out std_logic);
end BEDROCK;
architecture BEDROCK_MOORE of BEDROCK is
type STATE_TYPE is (BED, ROCK, RUN);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;
begin
STATE_REG: process(CLK, RESET_N)
begin
if(RESET_N = '0')then
CURRENT_STATE <= BED;
elsif(CLK'event and CLK = '1')then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;
NEXT_STATE_LOGIC: process(CURRENT_STATE, BARNEY, WILMA, MICE)
begin
case CURRENT_STATE is
when BED =>
if(MICE = '1')then
NEXT_STATE <= RUN;
elsif(BARNEY = '1')then
NEXT_STATE <= ROCK;
else
NEXT_STATE <= BED;
end if;
when ROCK =>
if(MICE = '1')then
NEXT_STATE <= RUN;
elsif(WILMA = '1')then
NEXT_STATE <= BED;
else
NEXT_STATE <= ROCK;
end if;
when RUN =>
if(MICE = '1')then
NEXT_STATE <= RUN;
elsif(WILMA = '1')then
NEXT_STATE <= BED;
elsif(BARNEY = '1')then
NEXT_STATE <= ROCK;
else
NEXT_STATE <= BED;
end if;
when others =>
NEXT_STATE <= BED;
end case;
end process;
OUTPUT_LOGIC: process(CURRENT_STATE)
begin
case CURRENT_STATE is
when BED =>
FRED <= '0';
DINO <= '0';
when ROCK =>
FRED <= '1';
DINO <= '0';
when RUN =>
FRED <= '1';
DINO <= '1';
when others =>
FRED <= '0';
DINO <= '0';
end case;
end process;
end BEDROCK_MOORE;
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